Array type discrete decoupling under bga grid

ABSTRACT

Various exemplary embodiments relate to a printed circuit board (PCB) for electrically connecting a discrete array component including a pattern formed on the PCB which is a merger of a set of via pads and a discrete array component; wherein the pattern is generated by a pin mapping between the discrete array component and a via grid array on the PCB; and wherein the pattern is formed of a metal etched during a manufacturing process of the PCB.

TECHNICAL FIELD

Various exemplary embodiments disclosed herein relate generally tocircuit board pad design.

BACKGROUND

A land grid array (LGA) is a type of surface-mount packaging (a chipcarrier) used for integrated circuits. LGA packages are used topermanently mount devices such as microprocessors. A LGA can providemore interconnection pins than can be put on a dual in-line or flatpackage. The whole bottom surface of the device can be used, instead ofjust the perimeter. A ball grid array (BGA) is a specific type of LGAthat uses solder balls to facilitate the connection between the deviceand a circuit board.

SUMMARY

A brief summary of various exemplary embodiments is presented. Somesimplifications and omissions may be made in the following summary,which is intended to highlight and introduce some aspects of the variousexemplary embodiments, but not to limit the scope of the invention.Detailed descriptions of a preferred exemplary embodiment adequate toallow those of ordinary skill in the art to make and use the inventiveconcepts will follow in later sections.

Various exemplary embodiments relate to a printed circuit board (PCB)for electrically connecting a discrete array component comprising: apattern formed on the PCB which is a merger of a set of via pads and adiscrete array component; wherein the pattern is generated by a pinmapping between the discrete array component and a via grid array on thePCB; and wherein the pattern is formed of a metal etched during amanufacturing process of the PCB.

Various exemplary embodiments relate to a computer aided design (CAD)tool implemented on a computing device for soldering a discrete arraycomponent on a printed circuit board (PCB) for use with mounting acomponent comprising: a design tool mode configured to identify aplacement of the discrete array component on the PCB and to verifywhether pin mapping between the discrete array component and a ball gridarray (BGA) on the opposite side of the PCB is feasible; a design toolmode configured to determine the geometry of a set of via pads to beassociated with the discrete array component and a geometry for thediscrete array component; and a design tool mode configured to generatea pattern on the PCB associated with a merger of the via pads anddiscrete array component.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to better understand various exemplary embodiments, referenceis made to the accompanying drawings, wherein:

FIG. 1A illustrates an exemplary outline of an array type component ontop of a via grid;

FIG. 1B illustrates exemplary side view of FIG. 1A;

FIG. 2 illustrates exemplary separate copper structures;

FIG. 3 illustrates an exemplary result of a merged copper patternbetween two different structures; and

FIG. 4 illustrates an exemplary solder mask application;

FIG. 5 illustrates an embodiment of a merged copper pattern;

FIG. 6 illustrates an embodiment of a merged copper pattern; and

FIG. 7 illustrates an exemplary method of merging copper patterns.

DETAILED DESCRIPTION

The description and drawings presented herein illustrate variousprinciples. It will be appreciated that those skilled in the art will beable to devise various arrangements that, although not explicitlydescribed or shown herein, embody these principles and are includedwithin the scope of this disclosure. As used herein, the term, “or”refers to a non-exclusive or (i.e,, and/or), unless otherwise indicated(e.g., “or else” or “or in the alternative”). Additionally, the variousembodiments described herein are not necessarily mutually exclusive andmay be combined to produce additional embodiments that incorporate theprinciples described herein. Further, while various exemplaryembodiments are described with regard to printed circuit boards (PCB).

Some embodiments include a merger of two different patterns on a PCB toallow the use of array type discrete on the back side of a PCB having aBGA on the directly opposite side. An array type discrete may include,for example, a plurality of resistors or capacitors. Similarly, avariety of both capacitors and resistors may be included on an arraytype discrete such as two resistors and one capacitor. Similarly, threeresistors may be attached to a single array type discrete.

Some components may include Land Grid Arrays (LGA) to connect to aPrinted Circuit Board (PCB). Solder paste may be applied in this case tothe PCB while the component is placed onto the correct position. Thesolder paste thereafter holds the component in the correct position. Ata later time, a soldering operation may be performed to fix thecomponent to the PCB.

Some components may have pads with pre-attached solder balls such as inball grid arrays (BGA's), and these may also need to be placed onto thecorresponding pads on the PCB. However with BGAs there may be twoalternatives—solder paste or flux, which may include solder-pastewithout the metallic component. Either the solder paste or the flux maystick the component in place until soldering occurs. Flux alone may beused because the solder of the “solder ball” of the BGA may provideenough solder to result in an electrical connection between thecomponent and the PCB. Once the component is soldered onto the boardthere may be no visibility or access to the pad which hold the solderjoints. The pads may be sheltered under the component.

In some or all of the embodiments, the PCB's may be made by thefollowing process:

Through-holes are produced in a circuit board. The holes may be coatedwith a conductive material, such as copper, producing a via barrel.Other via construction methods are recognized by those skilled in theart.

Adjacent vias may be entirely covered with etch resist. Etch resist maybe a thin layer of a nonconductive polymer which can resist the acidsused to remove copper from portions of the PCB. Via pads, via barrelsand through-holes may be seen after etching is complete and etch resistis removed. Component pads and solder mask may also be visible. Soldermask may be a thin layer of a nonconductive polymer. Solder mask mayprevent the copper portions of the via from oxidizing and preventsunintended solder bridges from accidentally forming on the circuitboard. Solder mask may be applied using a silkscreen process. Solderpaste may then be applied to a component pad within the boundaries ofsolder mask.

A portion of solder mask corresponding to a component landing area on acomponent pad may then be removed. This may be accomplished by etchingthe solder mask to remove material. In an exemplary embodiment soldermask may be modified using photolithography. However, other processesmay be used to remove a portion of solder the mask. Solder paste may beapplied to a component pad within the boundaries of the removed portionof solder mask.

A component may be attached to a component pad using reflowed solderpaste. Solder mask may act as a part of a barrier between the via padand component pad, preventing solder bridging from occurring during theattachment process.

Referring now to the drawings, in which like numerals refer to likecomponents or steps, there are disclosed broad aspects of variousexemplary embodiments.

FIG. 1A illustrates an exemplary outline of an array type component ontop of a via grid 100 on a PCB 106. FIG. 1A may include vias 102 in agrid pattern and array type component 104.

Some embodiments include a merger of two different structures on a PCB106 to allow the use of array type discretes on the back side of a PCBhaving a BGA on the directly opposite side. The first structure includesthe vias 102 which may belong to the part of the BGA grid for therouting of the BGA on the top side. The second structure may be referredto as a copper land pattern for an array type component, as outlined in104. These two structures did not share the same space in the PCB inprior methods, with the copper land pattern lying outside the BGA grid.In some embodiments, with pinout mapping between the two structures, themerger of the copper structure may be allowed to share the same space ona PCB.

FIG. 1B illustrates exemplary side view of FIG. 1A 150. Exemplary sideview 150 may include wrap plating 152, PCB base material 154, via fillmaterial 156, via wall plating 158, solder mask 160, discrete component162, and pins 164-168. Wrap plating 152 may include an electrolytic holdplating deposition which extends onto the surface of the PCB from aplated via structure. Wrap plating 152 may include copper plating from ahold which wraps around a surface foil.

PCB base material 154 may be any kind of base material such as Teflon,polyimide, FR4 high Tg, CEM1 etc. Via fill material 156 may be, forexample, copper plugs, copper plate, surface material, andnon-conductive epoxy. Solder mask 160 may be a thin layer of anonconductive polymer as described above. Solder mask may prevent thecopper portions of the via from oxidizing and prevents unintended solderbridges from accidentally forming on the circuit board. Solder mask maybe applied using a silkscreen process and be used to cover areas whichare not intended to be soldered.

Discrete component 162 may lay on top of the PCB as illustrated. Pins164-168 may overlap a typical BGA array pattern as illustrated where pin166 is not immediately above a via. As illustrated in the followingfigures, the pin mapping of the discrete array component(s) may includeany variety of geometry and patterning. For example, the same type ofarray component may be repeated on the PCB in a repeated pattern.Similarly, different array type components and/or patterning of thecomponent may be overlapped in development of the PCB. For example, useof a two capacitor array component may be repeated multiple times on onePCB. This would account for a similar pattern being repeated. Similarly,a PCB may account for one three resistor component, one two capacitorcomponent and one component with one resistor and one capacitor on it,such that the geometry of the three components on the PCB is not in afixed pattern.

FIG. 2 illustrates exemplary separate copper structures 200. Exemplarystructures 200 may include copper design vias 202, discrete componentcopper land pattern 204, and PCB 206. The two independent structuresshown in FIG. 2 are designed for the via grid for the BGA which mayprotrude from both sides of the PCB and for the array type discretecomponent.

As shown in FIG. 1A, four of the vias of the via grid array may map tothe four corner pins of the array type discrete while the two pins inthe middle array type discreet may map to two vias as shown and mayallow for the grounding of the device. Some embodiments may overlay thedesign the two copper structures, i.e., the via grid array and thecopper land pattern, which under normal circumstances may take up spaceseparately on the PCB 106.

FIG. 3 illustrates an exemplary result of a merged copper patternbetween two different copper structures 300. FIG. 3 illustrates theresult of the two copper structures of FIG. 2 overlayed on top of eachother.

FIG. 4 illustrates an exemplary solder mask application 400. Exemplarysolder mask application 402 may include solder mask 402. A solder mask402 may cover an exemplary area which is not intended be soldered. Thissolder mask 402 may allow an array type discrete component to be put onthe back side of a BGA and seeks to minimize the chance of shortsbetween adjacent copper pads.

FIG. 5 illustrates an embodiment of a merged copper pattern 500.Embodiment 500 may include merged copper pattern 502, vias 504, and PCB506. Copper pattern 502 may be spread over a 4×5 via grid as depicted.The copper pattern 502 has four corner pads that align with four cornervias of the 4×5 via grid. Embodiment 500 may also include a middlecopper layer 508 which may be spread over a 2×4 layer.

FIG. 6 illustrates another embodiment of a merged copper pattern 600.Embodiment 600 may include pads 602, 604, 606, 608, 610, 612, 614, 616,vias 620, and PCB 618. As is illustrated, the pads may be distributeddifferently. For example, pads 602 and 610 may be a pair, while pads 604and 612 may be another pair. The pad pairs may be separated by differentamount of vias as illustrated.

FIG. 7 illustrates an exemplary method of merging copper patterns 700.Method 700 may begin at step 702 where a CAD tool may be used or a PCBmay be created by this method. Method 700 may proceed to step 704 wherethe method may identify the placement of one or more discrete arraycomponents on the PCB.

Method 700 may then proceed to step 706 where it may verify the pinmapping between discrete components and the BGA. The discrete componentmay be made up of any number of components such as capacitors and/orresistors and may have any number of pins. Similarly, the discrete arraycomponent may be any size or geometry such as illustrated in FIG. 5-6.The method may then proceed to step 708.

In step 708 the method may determine the geometry of the via pads anddiscrete component(s). The method may then proceed to step 710. In step710 the CAD tool or PCB manufacturer may generate one or more patternswhich may include the merged via pads and one or more discretecomponents. In step 710, the generated pattern may be analyzed todetermine the portions of the generated pattern to be masked by soldermask. The method may then proceed to step 712 where it may stop.

The pattern generated by the method of merging copper patterns 700 maythen be used in a manufacturing process to form such a generated patternon the via side of the PCB. Then the manufacturing process may maskportions of the formed copper patter using solder mask.

In an exemplary embodiment, a computer aided design (CAD) tool allowsthe selection of vias and arrangement of the solder mask, componentpads, and vias to be substantially automated. The computer aided designtool may automatically identify appropriate spacing and shape of thesolder pad so as to allow placement of the surface mount components onthe printed circuit board. The CAD tool may also automatically test andmerge copper patterns in their design on top of a PCB as describedabove. A CAD tool may also provide instructions to control a machine tomanufacture the modified circuit board. Instructions may be exported tothe machine or the design tool may directly control the machine.

The CAD instructions may include any Electronic Design Automation toolor technique. For example, mask data preparation (MDP) may be used suchas generation of lithography photomasking which may be used tomanufacture a circuit or chip. Resolution enhancement techniques toincrease the photomask quality may also be used. Similarly, OptimalProximity Correction (OPC) for compensation of interference anddiffraction may be utilized. Mask generation may also be utilized in themanufacturing. Software systems and versions such as Advanced DesignSystem, Altium Designer, CircuitLogix, CircuitMaker, DesignSpark PCB,Pulsonix, SLED and Micro-Cap may be used or programmed for creation andautomation of such circuits.

It should be apparent from the foregoing description that variousexemplary embodiments of the invention may be implemented in hardwareand/or firmware. Furthermore, various exemplary embodiments may beimplemented as instructions stored on a machine-readable storage medium,which may be read and executed by at least one processor to perform theoperations described in detail herein. A machine-readable storage mediummay include any mechanism for storing information in a form readable bya machine, such as a personal or laptop computer, a server, or othercomputing device. Thus, a machine-readable storage medium may includeread-only memory (ROM), random-access memory (RAM), magnetic diskstorage media, optical storage media, flash-memory devices, and similarstorage media.

It should be appreciated by those skilled in the art that any blockdiagrams herein represent conceptual views of illustrative circuitryembodying the principals of the invention. Similarly, it will beappreciated that any flow charts, flow diagrams, state transitiondiagrams, pseudo code, and the like represent various processes whichmay be substantially represented in machine readable media and soexecuted by a computer or processor, whether or not such computer orprocessor is explicitly shown.

Although the various exemplary embodiments have been described in detailwith particular reference to certain exemplary aspects thereof, itshould be understood that the invention is capable of other embodimentsand its details are capable of modifications in various obviousrespects. As is readily apparent to those skilled in the art, variationsand modifications can be affected while remaining within the spirit andscope of the invention. Accordingly, the foregoing disclosure,description, and figures are for illustrative purposes only and do notin any way limit the invention, which is defined only by the claims.

1. A printed circuit board (PCB) for electrically connecting a discretearray component comprising: a pattern formed on the PCB including aplurality of merged pads, wherein the merged pads are via pads anddiscrete array component pads; wherein each merged pad is determined bya pin mapping between the discrete array component and a via grid arrayon the PCB that associates a discrete array pad with a via pad: whereineach merged pad is based upon a shape of the associated via pad and thediscrete array component pad; and wherein the pattern is formed of ametal etched during a manufacturing process of the PCB.
 2. The PCB ofclaim 1, wherein the PCB includes a plurality of the patterns formed onthe PCB.
 3. The PCB of claim 1, wherein the discrete array componentincludes a plurality of pins.
 4. The PCB of claim 1, wherein the PCBincludes a plurality of different patterns etched on the PCB.
 5. The PCBof claim 1, wherein the metal is copper.
 6. The PCB of claim 1, whereinthe pattern is generated by having verified that a pin mapping betweenthe discrete array component and a ball grid array on an opposite sideof the PCB is feasible.
 7. A computer aided design (CAD) toolimplemented on a computing device for soldering a discrete arraycomponent on a printed circuit board (PCB) for use with mounting acomponent comprising: a design tool mode configured to identify aplacement of the discrete array component on the PCB and to verifywhether pin mapping between the discrete array component and a ball gridarray (BGA) on the opposite side of the PCB is feasible; a design toolmode configured to determine the geometry of a set of via pads to beassociated with the discrete array component and a geometry for thediscrete array component; and a design tool mode configured to generatea pattern on the PCB associated with a merger of the via pads anddiscrete array component.
 8. The CAD tool of claim 7, wherein thediscrete component is made up a plurality of components.
 9. The CAD toolof claim 8, wherein the plurality of components include resistors,capacitors, diodes, transistors, and other small form factor discretedevices.
 10. The CAD tool of claim 7, wherein the discrete component ismade up of a plurality of pins.
 11. The CAD tool of claim 7, wherein thediscrete component may be any size or geometry.
 12. The CAD tool ofclaim 7, wherein the pattern is analyzed to determine the portions ofthe generated pattern to be masked by solder mask.
 13. The PCB of claim1, wherein the spacing between the discrete pads is different than thespacing between the via pads.
 14. A printed circuit board (PCB) forelectrically connecting a discrete array component comprising: a patternformed on the PCB which is a merger of a set of via pads and a discretearray component, the discrete array component having at least a 2 X 2grid; wherein the pattern is generated by a pin mapping between thediscrete array component and a via grid array on the PCB, wherein thepattern is formed of a metal etched during a manufacturing process ofthe PCB.
 15. The PCB of claim 14, wherein the spacing between thediscrete pads is different than the spacing between the via pads.